Multifunctional steep-slope spintronic transistors with spin-gapless-semiconductor or spin-gapped-metal electrodes

Abstract

Spin-gapless semiconductors (SGSs) are emerging as a promising class of materials for spintronic applications, offering unique opportunities to realize functionalities beyond conventional electronics. In this work, we propose a concept of multifunctional spintronic field-effect transistors (FETs) using SGSs and/or spin-gapped metals (SGMs) as source and drain electrodes. These devices operate similarly to metal-semiconductor Schottky-barrier FETs, where a potential barrier forms between the SGS (or SGM) electrode and the intrinsic semiconducting channel; however, unlike conventional Schottky-barrier FETs, our proposed devices exploit the distinctive spin-dependent transport properties of SGS and SGM electrodes to achieve sub-60-mV/dec switching, significantly surpassing the 60 mV/dec subthreshold swing (SS) limit in traditional MOSFETs, thereby enabling low-voltage operation. Additionally, the proposed FETs exhibit a nonlocal giant magnetoresistance (GMR) effect, enhancing functionality by enabling nonvolatile memory capabilities. The incorporation of SGMs also introduces a negative differential resistance effect with an ultrahigh peak-to-valley current ratio, further expanding the device’s multifunctionality. Two-dimensional (2D) nanomaterials provide a promising platform for realizing these advanced FETs. We perform a comprehensive screening of the computational 2D materials database to identify suitable SGS and SGM candidates. Among the materials identified, several exhibit Curie temperatures significantly above room temperature, ensuring robust ferromagnetic properties for practical applications. For device simulations, we select VS2 as the SGS material and, as a proof of concept, employ a nonequilibrium Green’s function method combined with density functional theory to simulate the transfer (𝐼D-𝑉G) and output (𝐼D-𝑉D) characteristics of a vertical VS2/Ga2O2 heterojunction FET. Our calculations predict a remarkably low SS of 20 mV/dec, a high on-off ratio of 108, and a significant nonlocal GMR effect, demonstrating the potential of these devices for low-power, high-performance logic and memory applications.